Graphical modeling and simulation environments or tools allow users to construct and analyze models of processes or systems using diagrams. There are various examples of such tools commercially available. One such example is Simulink/Stateflow from The MathWorks, Inc. which is a popular commercial model-based development tool for many industrial domains. A further example of a graphical modeling and simulation environments is LabVIEW, available from National Instruments Corporation.
Typically, these diagrams describe computations or logic which can ultimately be implemented using application specific devices, computers, microcontrollers, FPGAs, integrated circuits, or computing devices. The diagrams are built using elements or blocks which are interconnected. The diagrams are created within a graphical modeling environment which defines the semantics for executing the diagrams. Software systems or descriptions of hardware systems may then be produced which exhibit the behavior of the model or portions thereof.
Although Simulink/Stateflow is designed for the simulation of the designs, it does not provide a model that makes it amenable for formal analysis such as verification and validation. For safety and security concerns, verification and testing must be performed on the Simulink/Stateflow designs and the generated code. What is needed is a way to translate a Stateflow chart into an Input/Output Extended Finite Automata (I/O-EFA) model which preserves discrete behaviors. Moreover, what is further needed is an automatic test generation approach for Simulink/Stateflow based on its translation to Input/Output Extended Finite Automata (I/O-EFA).